Five-stage RV32I-subset core
12 fetch-boundary cases across six timing setups: 72 passing simulation runs.
See checks, logs and testbench ↗HELLO, I'M ADAM MORGAN
Engineering from the logic gate up.
I’m an Electrical Engineering student at Toronto Metropolitan University, interested in RTL design and verification. I’m building a five-stage RISC-V processor in SystemVerilog and testing how it handles hazards, memory delays, and faults.
Expected graduation: 2030 · Seeking RTL design & verification co-op opportunities
Verification first: See the processor tests, source, and results ↗
START HERE / INSPECTABLE ENGINEERING
Design claims, with receipts.
Synchronous FIFO
Four RTL configurations checked against an independent scoreboard, with a generic synthesis check.
Inspect assertions and VCD ↗Cache mapping model
Eight automated checks reproduce the software model’s mapping and replacement behavior.
Inspect reproducible results ↗01 / SELECTED WORK
Things I've built & am building.
The most useful proof is work you can inspect. Start with the processor case study, then follow the source, testing approach and project notes.
01COMPUTER ARCHITECTURE / RTLFETCH BOUNDARY / FAULT-STOP TESTS
32-bit RISC-V processor core
A five-stage RV32I-subset CPU in SystemVerilog with independent instruction/data ports and an opt-in fail-stop path. New fetch-boundary simulations demonstrate ordered faults at the modeled 4 KiB instruction limit, older-instruction completion, and suppression of tested speculative wrong-path faults.
What you can inspect now
- Fetch boundsAn invalid fetch PC becomes a squashable IF-to-EX fault token (cause 1), not an out-of-range external instruction request.
- New verification12 fetch-boundary scenarios across six timing configurations; results and reproduction commands are linked in the case study.
- StatusVerified in simulation. Synthesis and FPGA deployment are future processor milestones.
ARCHITECTURE OVERVIEWRV32I / 5 STAGES
IFFetch
IDDecode
EXExecute
MEMMemory
WBWriteback
Fetch buffers one returned instruction; older data transactions hold younger stages. Both memory channels are exercised by an independent simulation adapter.
ISATested RV32I subset
LANGUAGESystemVerilog
TESTINGFetch boundary + fault ordering
FPGAFuture target
Engineering notes
Independent I/D ready/valid ports and an opt-in sticky halt remain. Fetches outside the local 4 KiB model create an age-ordered fault token; a taken branch or jump at 0xffc can discard it, while a legal jump to 0x1000 retires its link before the younger fetch faults. Older data requests drain, and no out-of-range external I request is offered. These are simulation diagnostics, not machine-mode traps.
FROM THE RTL WORKBENCH / VERIFICATION
A small queue. A lot of edge cases.
A parameterized single-clock FIFO in SystemVerilog, checked against an independent scoreboard. Four depth/width configurations pass directed and deterministic randomized tests.
RTL SIMULATION + GENERIC SYNTHESIS
Read the FIFO case study
Browse real RTL
View passing simulator log
Follow one FIFO boundary test
02COMPUTER ARCHITECTURE / MEMORY
Cache memory lab
Built a configurable cache lookup model to compare address mapping, associativity and replacement decisions—with repeatable traces and automated tests.
- Model
- Direct-mapped · 2-way · LRU/FIFO
- Tests
- 8 automated checks · reference comparison
- Evidence
- Source · test suite · generated results
MODEL HIT RATES · 0% / 97.92%
What the experiment showed
On a 96-access synthetic conflict trace, the 128-byte direct-mapped cache had a 0% hit rate, compared with 97.92% for the equally sized two-way cache. This is model output, not real CPU performance.
03EMBEDDED SYSTEMS
Tendon-driven robotic hand
Prototype work exploring 3D-printed mechanical parts, an ESP32, servo actuation and tendon-driven movement. The public render illustrates a design direction; it is not evidence of the assembled hardware.
- Hardware
- ESP32 · servo motors
- Design areas
- CAD · tendon routing · joint geometry
- Challenge
- Friction, tension and consistent movement
ROUGH 3D ASSEMBLY STUDY
Project notes
Designing around the relationship between actuator torque, printed parts, and cable tension reinforced how tightly mechanical and electrical design are connected. Improved sensing and more sophisticated control are future directions.
Prototype work · no public as-built photos, measured CAD or motion-test results yet
04LINUX / INFRASTRUCTURE
A practical home server
Repurposed a compact office PC into an Ubuntu server for a personal Immich photo archive, Tailscale access and self-hosted tools.
- Hardware
- HP EliteDesk · Core i5-8500
- System
- Ubuntu · 4 TB media HDD
- Networking
- Tailscale · self-hosted services
64 GB RAM REPORTED / LINUX INVENTORY
Project notes
Working on a live system taught me about backups, storage layout, network reliability, Linux maintenance and safe remote access. I use it as practical infrastructure for other projects.
05PRODUCT / WEB APPLICATION
Haven Education
A student workflow app bringing course planning, coursework, focus sessions and progress into one place.
- Frontend
- React · JavaScript
- Focus
- Responsive student workflows
- Approach
- State, testing and iteration
ACTUAL HAVEN UI / DEMO DATA
Project notes
The problem I’m working on is making it easier to move from knowing what is due to actually choosing and starting useful study work. Course and task context are central to the product.
FROM THE NOTEBOOKEvidence, decisions & iteration
Beyond the project card.
A closer look at three different problems: processor verification, reliable personal infrastructure, and the study workflows behind Haven Education.
02 / MY JOURNEY
Curiosity has a timeline.
Progress from fundamentals toward practical systems shows what I'm learning and why I keep building.
2026Building systems I can test
RISC-V and verification
Developing a 32-bit RV32I-subset processor prototype in SystemVerilog, moving from standalone ALU tests to self-checking integrated instruction-program simulations. Read the case study ↗
Linux and self-hosting
Turning refurbished hardware into personal storage, remote infrastructure and a place to experiment with automation. Explore the setup ↗
Product thinking
Developing Haven Education to connect coursework, study planning and practical student workflows. Explore the case study ↗
2025Strengthening the fundamentals
Working from first principles
Reinforcing the mathematics, programming and engineering foundations that support later hardware work.
Exploring digital design
Building an interest in reusable logic modules, hardware description languages and simulation as a way to understand circuits.
2024From theory toward hardware
Engineering fundamentals
Studying mathematics, physics and programming while exploring how a digital system is assembled from smaller components.
First experiments
Growing more interested in electronics, digital logic and the connection between software instructions and physical behavior.
2023The beginning at TMU
Starting engineering
Beginning my engineering education at Toronto Metropolitan University and discovering how much there is to learn across hardware, computing and design.
03 / ABOUT
I want to know why it works.
What I’m working toward
I study electrical engineering at TMU, with an expected graduation in 2030. I’m particularly interested in processor microarchitecture, digital design, and the bridge between circuit-level behavior and computer systems.
I like working from first principles, building a prototype, and understanding why it behaves the way it does. That applies whether I’m examining an RTL waveform, troubleshooting a circuit, or maintaining a Linux server.
Outside engineering, I play piano and run an independent design business. Working across hardware and physical products keeps me curious about how ideas become things people use.
Connect on LinkedIn ↗Tools & areas I work with
Digital systems
Boolean logic, sequential circuits, processor datapaths
RTL & simulation
SystemVerilog, Verilog, Icarus Verilog, GTKWave
Hardware tools
Quartus, ModelSim, FPGA coursework
Software
C, Java, Python, Git, Linux, React
Areas of interest and experience at different stages of development — see project evidence for depth.
04 / OUTSIDE THE LAB
The person behind the projects.
Engineering is also communication, judgment, and following a problem through to a useful result.
Public Services and Procurement Canada
Working in customer support has reinforced the importance of clear communication, consistent processes, attention to detail and reliability when other people depend on your answer.
Client support · National Service Call CentreChristlike
Since 2022, I've developed a clothing brand from design concepts into manufactured products. Creating technical packs, choosing materials and coordinating with suppliers taught me to turn an idea into a specification someone else can build.
Design · Manufacturing · OwnershipMore background and current experience are available on LinkedIn ↗.
05 / CONNECT
Let's talk hardware.
I’m pursuing RTL design, design verification, and digital hardware co-op roles. Expected graduation: 2030. Please contact me to discuss start dates and term length.