ADAM_MORGAN // ELECTRICAL_ENGINEERING

Hi, I'm Adam.
I design digital systems and computer processors.

Currently Working On:

Electrical Engineering @ TMU

Focused on processor architecture, RTL design, FPGA development, and digital systems.

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FEATURED_PROJECT // PROCESSOR_DESIGN
COMPUTER_ARCHITECTURE // RTL

32-Bit Pipelined RISC-V CPU Core

IF
ID
EX
MEM
WB
RV32I

FEATURES

  • 32-bit RV32I ISA
  • 5-stage pipeline
  • Hazard detection
  • Forwarding logic
  • RTL simulation
  • FPGA target

CURRENT STATUS

Design
80%
Verification
70%
Documentation
50%
UPDATE // JULY 19, 2026

I'm excited to share a major milestone in my summer processor project: I have successfully designed and verified the Arithmetic Logic Unit for my 32-bit RISC-V CPU core. What started as a datapath concept is now a functional, tested RTL module handling arithmetic, logical, comparison, and shift operations.

The biggest shift in this phase was moving beyond manual waveform inspection and building automated, self-checking SystemVerilog testbenches. Seeing the simulation end with "ALL ALU TESTS PASSED!" after exercising edge cases, signed and unsigned behavior, zero detection, and operation decoding was a huge step forward in how I verify hardware.

  • Verification: self-checking testbenches make the design loop faster and more reliable.
  • Automation: using iverilog and vvp streamlined repeatable ALU regression testing.
  • Precision: signed/unsigned comparisons, shifts, overflow thinking, and the zero flag all matter at the ISA level.

Theoretically, the ALU is where the instruction set starts becoming real hardware: control signals, operands, flags, and datapath timing all meet in one block. Next, I will integrate it into the execution stage, connect it with pipeline control, and keep pushing toward finishing the full processor.

This project took me through the real engineering tradeoffs behind processor design: turning an instruction set into datapaths, control logic, timing boundaries, hazards, forwarding paths, and verification signals that could be reasoned about cycle by cycle.

I learned how performance depends on disciplined architecture decisions, not just code: clean pipeline stages, predictable control, simulation-driven debugging, and the ability to connect low-level RTL behavior to the kind of efficient compute systems that matter at AMD, NVIDIA, and Qualcomm.

RV32I RTL Design Pipeline Architecture Hazard Forwarding Waveform Simulation
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PROJECT // ROBOTIC_PROSTHETIC_HAND
ROBOTICS // EMBEDDED_SYSTEMS // MECHANICAL_DESIGN

Tendon-Driven Robotic Prosthetic Hand

Built a functional robotic hand prototype using 3D-printed parts, tendon routing, servo actuation, and an ESP32 controller to create lightweight finger movement inspired by human biomechanics.

The main engineering challenge was making the hand feel mechanically simple while still moving like a coordinated system: tendon tension, servo timing, joint friction, and part stiffness all had to work together instead of being solved separately.

  • Designed tendon paths and mechanical joints to reduce actuator complexity
  • Iterated through friction, alignment, grip consistency, and durability issues
  • Integrated sensor feedback toward more adaptive object handling
  • Tuned servo movement so multiple fingers could close with a more consistent grip
  • Balanced printed part strength, weight, and available actuator torque

This project helped me connect embedded control with real mechanical constraints. I learned how small changes in CAD geometry, tendon routing, and feedback logic can completely change the reliability of the final system.

ESP32 Embedded C/C++ Servo Control Force Sensing CAD + 3D Printing

Future: EMG control, custom PCB integration, and improved actuator efficiency.

ABOUT // ADAM

About Adam

I'm an Electrical Engineering student at TMU focused on processor architecture, digital systems, and FPGA development.

I enjoy understanding how computers work from first principles and building hardware that solves real engineering problems.

Outside engineering, I spend my time playing piano, building personal projects, and continuously learning new technologies.

JOURNEY // ENGINEERING

Select a year to see the progression.

Select a year to see the progression.

TECHNICAL_STACK // TOOLS

LANGUAGES/

SystemVerilog Verilog C C++ C# Java Python HTML/CSS/JavaScript

HARDWARE/

FPGA Digital Logic Processor Design Computer Architecture

TOOLS/

Quartus ModelSim GTKWave Git VS Code
CURRENT_FOCUS // RTL

Current Focus

ENGINEERING // PHILOSOPHY

Engineering Philosophy

CURRENTLY_LEARNING // COMPUTER_ARCHITECTURE

Currently Learning

Computer Architecture Digital Design & Computer Architecture RISC-V Specification Modern Processor Design Branch Prediction Pipeline Optimization
ENTREPRENEURSHIP // PRODUCT

Entrepreneurship

Designed and launched an independent consumer product while managing manufacturing, supplier communication, budgeting, branding, and product strategy.

This experience strengthened my project management, problem-solving, and decision-making skills beyond engineering.

CONNECT // LINKS
GitHub LinkedIn Resume Email