FIFO RTL self-checking regression | Icarus Verilog 12.0 | 2026-10-14
Reproduce: bash projects/fifo-rtl/run_tests.sh
Directed boundaries + 800 deterministic pseudo-random cycles per configuration
Lines below are the actual selected simulator output (temporary local paths omitted).

--- FIFO DEPTH=1 DATA_WIDTH=8 ---
VCD info: dumpfile fifo_depth1_width8.vcd opened for output.
PASS sync_fifo WIDTH=8 DEPTH=1 cycles=814 writes=288 reads=287 blocked_write=132 blocked_read=151
--- FIFO DEPTH=3 DATA_WIDTH=8 ---
VCD info: dumpfile fifo_depth3_width8.vcd opened for output.
PASS sync_fifo WIDTH=8 DEPTH=3 cycles=820 writes=370 reads=369 blocked_write=52 blocked_read=73
--- FIFO DEPTH=4 DATA_WIDTH=8 ---
VCD info: dumpfile fifo_depth4_width8.vcd opened for output.
PASS sync_fifo WIDTH=8 DEPTH=4 cycles=823 writes=385 reads=384 blocked_write=38 blocked_read=60
--- FIFO DEPTH=8 DATA_WIDTH=16 ---
VCD info: dumpfile fifo_depth8_width16.vcd opened for output.
PASS sync_fifo WIDTH=16 DEPTH=8 cycles=835 writes=413 reads=412 blocked_write=14 blocked_read=40
PASS four FIFO parameter configurations