HISTORICAL CHECKPOINT — independent standalone RISC-V module checks
Recorded: 2026-10-14
Source: https://github.com/byadmo/riscv_core
Source commit: 36e048da6760d1d0179f6dea412a9e7f5f5656d7
Simulator: Icarus Verilog 12.0 (unpacked locally, no global installation)
Scope: individually selected standalone SystemVerilog module testbenches; not a full CPU simulation.
This record describes the early standalone-only revision above, not the
current processor implementation. Later integrated program results are in
rv32i-integrated-results.txt, with subsequent fetch/fault milestones in
fetch-fault-results.txt and fault-halt-results.txt.

$ unpacked/usr/bin/vvp tb_alu.vvp
VCD info: dumpfile alu_sim.vcd opened for output.
tb_alu PASS
../riscv-evidence/tb/tb_alu.sv:71: $finish called at 11000 (1ps)
Exit code: 0

$ unpacked/usr/bin/vvp tb_register_file.vvp
VCD info: dumpfile register_file_sim.vcd opened for output.
tb_register_file PASS
../riscv-evidence/tb/tb_register_file.sv:115: $finish called at 67000 (1ps)
Exit code: 0

$ unpacked/usr/bin/vvp tb_control_unit.vvp
VCD info: dumpfile control_unit_sim.vcd opened for output.
tb_control_unit PASS
../riscv-evidence/tb/tb_control_unit.sv:82: $finish called at 9000 (1ps)
Exit code: 0

Reproduce from the public riscv_core repository root with an installed Icarus Verilog 12:
  iverilog -g2012 -s tb_alu -o /tmp/tb_alu.vvp rtl/alu.sv tb/tb_alu.sv
  vvp /tmp/tb_alu.vvp
  iverilog -g2012 -s tb_register_file -o /tmp/tb_register_file.vvp rtl/register_file.sv tb/tb_register_file.sv
  vvp /tmp/tb_register_file.vvp
  iverilog -g2012 -s tb_control_unit -o /tmp/tb_control_unit.vvp rtl/control_unit.sv tb/tb_control_unit.sv
  vvp /tmp/tb_control_unit.vvp
Commands above express the same selected sources and tops used for the observed module results.
The local vvp commands shown earlier used an unpacked package's binary and precompiled testbench files.
No test has been altered to produce these PASS outputs.
The combined scripts/run_all_tests.ps1 does not establish these individual passes.
Historical limitation at commit 36e048da only: rtl/pipeline_core.sv failed
compilation at an invalid module-scope assignment (line 148). At this
standalone-only checkpoint, integrated CPU operation was not yet demonstrated.
Later revisions fixed this issue and passed actual integrated instruction
regressions; see rv32i-integrated-results.txt for separate later evidence.
No synthesis, timing, area, power or FPGA results are claimed by this log.
Raw waveform: /assets/verification/alu_sim.vcd