Integrated RV32I-subset self-checking regression | Icarus Verilog 12.0 | 2026-10-14
Reproduce: bash scripts/run_regression.sh /tmp/rv32i-evidence
Output below preserves actual PASS and Observed lines from simulator stdout, removing host filesystem paths.
Interpretation: four architectural instruction programs plus one separate control-flow program, and three standalone module testbenches.

--- alu ---
tb_alu PASS
--- register_file ---
tb_register_file PASS
--- control_unit ---
tb_control_unit PASS
--- integrated architectural programs ---
PASS ALU, immediates, forwarding (34 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS loads, stores, RAW stalls (31 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS branches, redirects, flush (53 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS load to branch / flush   (21 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS ALL: 4 integrated RV32I programs, 4224 architectural state checks
Observed: 7 load-use stalls, 11 taken branch redirects
--- independent control-flow program ---
PASS controlflow: U/J, signed/unsigned branches, redirect flush, JALR alignment, x0
PASS regression: 3 standalone modules + 4 integrated programs + 1 control-flow program