Icarus Verilog 12, 2026-10-14 Tested source tree 117cccf60bbf2f9d195772b3ef982ff51ad0834a Reproduce: bash scripts/run_regression.sh /tmp/rv32i-evidence Below is actual simulator stdout with only host-specific paths normalized. --- alu --- VCD info: dumpfile alu_sim.vcd opened for output. tb_alu PASS /tb/tb_alu.sv:71: $finish called at 11000 (1ps) --- register_file --- VCD info: dumpfile register_file_sim.vcd opened for output. tb_register_file PASS /tb/tb_register_file.sv:115: $finish called at 67000 (1ps) --- control_unit --- VCD info: dumpfile control_unit_sim.vcd opened for output. tb_control_unit PASS /tb/tb_control_unit.sv:82: $finish called at 9000 (1ps) --- integrated architectural programs --- Writing integrated RV32I waveform to /rv32i_integrated.vcd VCD info: dumpfile /rv32i_integrated.vcd opened for output. PASS ALU, immediates, forwarding (34 cycles to PC past end, 32 regs and 1024 memory words checked) PASS loads, stores, RAW stalls (42 cycles to PC past end, 32 regs and 1024 memory words checked) PASS branches, redirects, flush (53 cycles to PC past end, 32 regs and 1024 memory words checked) PASS load to branch / flush (25 cycles to PC past end, 32 regs and 1024 memory words checked) PASS ALL: 4 integrated RV32I programs, 4224 architectural state checks Observed: 13 load-use stalls, 11 taken branch redirects /tb/tb_integrated_rv32i.sv:421: $finish called at 1940000 (1ps) --- independent control-flow program --- VCD info: dumpfile rv32i_controlflow.vcd opened for output. PASS controlflow: U/J, signed/unsigned branches, redirect flush, JALR alignment, x0 /tb/tb_controlflow_rv32i.sv:60: $finish called at 930000 (1ps) PASS regression: 3 standalone modules + 4 integrated programs + 1 control-flow program --- latency-aware memory and independent reference regressions --- --- Directed memory latency 1 extra 0 --- PASS DATA_LATENCY=1 extra=0 back-to-back LW/SW, RAW and address cycles=36 req/rsp=12/12 stores=6 PASS DATA_LATENCY=1 extra=0 consecutive delayed loads and stores cycles=29 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=0 loads + redirect + wrong-path stores cycles=43 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=0 loaded loop bound and backward branch cycles=30 req/rsp=5/5 stores=2 PASS DATA_LATENCY=1 extra=0 reset during pending memory store cycles=13 req/rsp=3/3 stores=1 PASS DATA_LATENCY=1 extra=0 byte/halfword sign extension and lanes cycles=45 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=1 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 3260000 (1ps) --- Directed memory latency 1 extra 3 --- PASS DATA_LATENCY=1 extra=3 back-to-back LW/SW, RAW and address cycles=52 req/rsp=12/12 stores=6 PASS DATA_LATENCY=1 extra=3 consecutive delayed loads and stores cycles=38 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=3 loads + redirect + wrong-path stores cycles=52 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=3 loaded loop bound and backward branch cycles=36 req/rsp=5/5 stores=2 PASS DATA_LATENCY=1 extra=3 reset during pending memory store cycles=16 req/rsp=3/3 stores=1 PASS DATA_LATENCY=1 extra=3 byte/halfword sign extension and lanes cycles=75 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=1 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 3990000 (1ps) --- Directed memory latency 2 extra 0 --- PASS DATA_LATENCY=2 extra=0 back-to-back LW/SW, RAW and address cycles=48 req/rsp=12/12 stores=6 PASS DATA_LATENCY=2 extra=0 consecutive delayed loads and stores cycles=38 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=0 loads + redirect + wrong-path stores cycles=52 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=0 loaded loop bound and backward branch cycles=35 req/rsp=5/5 stores=2 PASS DATA_LATENCY=2 extra=0 reset during pending memory store cycles=16 req/rsp=3/3 stores=1 PASS DATA_LATENCY=2 extra=0 byte/halfword sign extension and lanes cycles=64 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=2 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 4080000 (1ps) --- Directed memory latency 2 extra 3 --- PASS DATA_LATENCY=2 extra=3 back-to-back LW/SW, RAW and address cycles=64 req/rsp=12/12 stores=6 PASS DATA_LATENCY=2 extra=3 consecutive delayed loads and stores cycles=47 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=3 loads + redirect + wrong-path stores cycles=61 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=3 loaded loop bound and backward branch cycles=41 req/rsp=5/5 stores=2 PASS DATA_LATENCY=2 extra=3 reset during pending memory store cycles=19 req/rsp=3/3 stores=1 PASS DATA_LATENCY=2 extra=3 byte/halfword sign extension and lanes cycles=94 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=2 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 4810000 (1ps) --- Directed memory latency 4 extra 0 --- PASS DATA_LATENCY=4 extra=0 back-to-back LW/SW, RAW and address cycles=72 req/rsp=12/12 stores=6 PASS DATA_LATENCY=4 extra=0 consecutive delayed loads and stores cycles=56 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=0 loads + redirect + wrong-path stores cycles=70 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=0 loaded loop bound and backward branch cycles=45 req/rsp=5/5 stores=2 PASS DATA_LATENCY=4 extra=0 reset during pending memory store cycles=22 req/rsp=3/3 stores=1 PASS DATA_LATENCY=4 extra=0 byte/halfword sign extension and lanes cycles=102 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=4 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 5700000 (1ps) --- Directed memory latency 4 extra 3 --- PASS DATA_LATENCY=4 extra=3 back-to-back LW/SW, RAW and address cycles=88 req/rsp=12/12 stores=6 PASS DATA_LATENCY=4 extra=3 consecutive delayed loads and stores cycles=65 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=3 loads + redirect + wrong-path stores cycles=79 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=3 loaded loop bound and backward branch cycles=51 req/rsp=5/5 stores=2 PASS DATA_LATENCY=4 extra=3 reset during pending memory store cycles=25 req/rsp=3/3 stores=1 PASS DATA_LATENCY=4 extra=3 byte/halfword sign extension and lanes cycles=132 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=4 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 6430000 (1ps) SEED 31415: 198 instructions, 191 sequential reference steps --- Reference seed 31415 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=333 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3620000 (1ps) --- Reference seed 31415 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=438 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4700000 (1ps) --- Reference seed 31415 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=506 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 5390000 (1ps) --- Reference seed 31415 latency 4 extra 3 --- VCD info: dumpfile /memory/memory_handshake.vcd opened for output. PASS random reference latency=4 extra=3 cycles=642 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6770000 (1ps) SEED 27182: 202 instructions, 194 sequential reference steps --- Reference seed 27182 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=328 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3570000 (1ps) --- Reference seed 27182 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=420 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4520000 (1ps) --- Reference seed 27182 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=479 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 5120000 (1ps) --- Reference seed 27182 latency 4 extra 3 --- PASS random reference latency=4 extra=3 cycles=597 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6320000 (1ps) SEED 16180: 196 instructions, 188 sequential reference steps --- Reference seed 16180 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=321 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3500000 (1ps) --- Reference seed 16180 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=408 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4400000 (1ps) --- Reference seed 16180 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=464 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4970000 (1ps) --- Reference seed 16180 latency 4 extra 3 --- PASS random reference latency=4 extra=3 cycles=576 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6110000 (1ps) --- Expected simulation rejection: memory fault 0 --- PASS expected rejection fault 0 --- Expected simulation rejection: memory fault 1 --- PASS expected rejection fault 1 --- Expected simulation rejection: memory fault 2 --- PASS expected rejection fault 2 --- Expected simulation rejection: memory fault 3 --- PASS expected rejection fault 3 PASS memory regression: 36 directed scenario runs (38016 state checks), 12 reference-program runs (12672 state checks), 4 expected fault rejections Actual logs and VCD: /memory Evidence and logs: