Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)
--- Generic synthesis DEPTH=1 DATA_WIDTH=8 ---

4.24. Executing CHECK pass (checking for obvious problems).
Checking module sync_fifo...
Found and reported 0 problems.

5. Executing CHECK pass (checking for obvious problems).
Checking module sync_fifo...
Found and reported 0 problems.

6. Printing statistics.

=== sync_fifo ===

   Number of wires:                 22
   Number of wire bits:             43
   Number of public wires:          13
   Number of public wire bits:      34
   Number of ports:                  9
   Number of port bits:             23
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 29
     $_AND_                          3
     $_DFFE_PN0P_                    9
     $_DFFE_PP_                      8
     $_NOT_                          5
     $_OR_                           4

7. Executing JSON backend.
--- Generic synthesis DEPTH=3 DATA_WIDTH=8 ---
Checking module sync_fifo...
Found and reported 0 problems.

5. Executing CHECK pass (checking for obvious problems).
Checking module sync_fifo...
Found and reported 0 problems.

6. Printing statistics.

=== sync_fifo ===

   Number of wires:                 54
   Number of wire bits:            132
   Number of public wires:          16
   Number of public wire bits:      54
   Number of ports:                  9
   Number of port bits:             24
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                113
     $_AND_                         22
     $_DFFE_PN0P_                   14
     $_DFFE_PP_                     24
     $_MUX_                         12
     $_NOT_                         17
     $_OR_                          20
     $_XOR_                          4

7. Executing JSON backend.
--- Generic synthesis DEPTH=4 DATA_WIDTH=8 ---
Checking module sync_fifo...
Found and reported 0 problems.

5. Executing CHECK pass (checking for obvious problems).
Checking module sync_fifo...
Found and reported 0 problems.

6. Printing statistics.

=== sync_fifo ===

   Number of wires:                 72
   Number of wire bits:            175
   Number of public wires:          17
   Number of public wire bits:      63
   Number of ports:                  9
   Number of port bits:             25
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                150
     $_AND_                         33
     $_DFFE_PN0P_                   15
     $_DFFE_PP_                     32
     $_MUX_                         12
     $_NOT_                         19
     $_OR_                          33
     $_XOR_                          6

7. Executing JSON backend.
--- Generic synthesis DEPTH=8 DATA_WIDTH=16 ---
Checking module sync_fifo...
Found and reported 0 problems.

5. Executing CHECK pass (checking for obvious problems).
Checking module sync_fifo...
Found and reported 0 problems.

6. Printing statistics.

=== sync_fifo ===

   Number of wires:                131
   Number of wire bits:            522
   Number of public wires:          21
   Number of public wire bits:     178
   Number of ports:                  9
   Number of port bits:             42
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                480
     $_AND_                        129
     $_DFFE_PN0P_                   26
     $_DFFE_PP_                    128
     $_MUX_                         22
     $_NOT_                         29
     $_OR_                         136
     $_XOR_                         10

7. Executing JSON backend.
PASS four generic FIFO synthesis configurations (no device mapping or timing claim)