FIFO controlled debugging exercise
Original DUT SHA-256: ab6f0712f0c44f84ab7cd2cd4cd5e4caabc92f2d6b63b661ea81690a4c07d91c
Method: deliberately remove the full+read exception from take_write.
The independent scoreboard and stimulus are unchanged in both runs.
This is a reproducible mutation exercise, not historical bug-discovery evidence.

[faulty] exit=1

VCD info: dumpfile fifo_depth4_width8.vcd opened for output.
FATAL: <repo>/projects/fifo-rtl/tb/tb_sync_fifo.sv:38: cycle=10 DEPTH=4 expected count/full/empty/data=4/1/0/1 actual=3/0/0/1
       Time: 136000  Scope: tb_sync_fifo.verify

[corrected] exit=0

VCD info: dumpfile fifo_depth4_width8.vcd opened for output.
PASS sync_fifo WIDTH=8 DEPTH=4 cycles=823 writes=385 reads=384 blocked_write=38 blocked_read=60
<repo>/projects/fifo-rtl/tb/tb_sync_fifo.sv:132: $finish called at 8296000 (1ps)

PASS defective logic rejected; existing corrected logic passes