--- fetch boundary fetch_e0_d1x0_i2x0_busd3x0_r0_hold0 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS fetch-fault ext=0 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=1027 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=11 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=12 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=9 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=10 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=8 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=0 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JAL at 0xffc redirects inward; link survives marker=42 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JALR at 0xffc redirects inward; link survives marker=43 cycles=12 Iheld=0 Dheld=0
PASS fetch-fault ext=0 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=0 sticky clear and fresh execution
PASS fetch-fault suite ext=0 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 18160000 (1ps)
--- fetch boundary fetch_e0_d2x3_i2x2_busd3x2_r1_hold0 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS fetch-fault ext=0 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=1027 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=18 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=14 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=9 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=10 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=8 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=0 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JAL at 0xffc redirects inward; link survives marker=42 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JALR at 0xffc redirects inward; link survives marker=43 cycles=12 Iheld=0 Dheld=0
PASS fetch-fault ext=0 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=0 sticky clear and fresh execution
PASS fetch-fault suite ext=0 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 19010000 (1ps)
--- fetch boundary fetch_e0_d4x3_i2x2_busd3x2_r1_hold0 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS fetch-fault ext=0 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=1027 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=22 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=18 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=9 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=10 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=0 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=8 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=0 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JAL at 0xffc redirects inward; link survives marker=42 cycles=11 Iheld=0 Dheld=0
PASS fetch-valid ext=0 JALR at 0xffc redirects inward; link survives marker=43 cycles=12 Iheld=0 Dheld=0
PASS fetch-fault ext=0 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=7 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=0 sticky clear and fresh execution
PASS fetch-fault suite ext=0 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 19250000 (1ps)
--- fetch boundary fetch_e1_d1x0_i2x2_busd3x2_r1_hold0 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS fetch-fault ext=1 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=7427 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=24 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=45 D=2 Iheld=1 Dheld=0
PASS fetch-fault ext=1 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=49 D=2 Iheld=5 Dheld=0
PASS fetch-fault ext=1 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=26 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=34 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=32 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=1 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=33 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JAL at 0xffc redirects inward; link survives marker=42 cycles=33 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JALR at 0xffc redirects inward; link survives marker=43 cycles=41 Iheld=0 Dheld=0
PASS fetch-fault ext=1 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=24 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=1 sticky clear and fresh execution
PASS fetch-fault suite ext=1 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 85090000 (1ps)
--- fetch boundary fetch_e1_d2x2_i4x3_busd1x4_r1_hold5 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
VCD info: dumpfile <scratch-output-dir>/fetch_fault_handshakes.vcd opened for output.
PASS fetch-fault ext=1 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=10243 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=30 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=57 D=2 Iheld=0 Dheld=3
PASS fetch-fault ext=1 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=57 D=2 Iheld=0 Dheld=0
PASS fetch-fault ext=1 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=32 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=42 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=40 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=1 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=44 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JAL at 0xffc redirects inward; link survives marker=42 cycles=44 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JALR at 0xffc redirects inward; link survives marker=43 cycles=51 Iheld=0 Dheld=0
PASS fetch-fault ext=1 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=30 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=1 sticky clear and fresh execution
PASS fetch-fault suite ext=1 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 116350000 (1ps)
--- fetch boundary fetch_e1_d4x3_i1x0_busd6x2_r1_hold5 ---
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS fetch-fault ext=1 1024 sequential words then fetch at 0x1000 cause=1 pc=tval=00001000 cycles=5465 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 last legal ADDI retires before sequential fault cause=1 pc=tval=00001000 cycles=18 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 SW+LW directly before invalid fetch drain older cause=1 pc=tval=00001000 cycles=45 D=2 Iheld=6 Dheld=0
PASS fetch-fault ext=1 delayed LW/load-use/SW drain before invalid fetch cause=1 pc=tval=00001000 cycles=47 D=2 Iheld=8 Dheld=0
PASS fetch-fault ext=1 JAL at 0xffc to 0x1000 links then fetch faults cause=1 pc=tval=00001000 cycles=20 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 JALR at 0xffc to 0x1000 links then faults  cause=1 pc=tval=00001000 cycles=25 D=0 Iheld=0 Dheld=0
PASS fetch-fault ext=1 not-taken BEQ at 0xffc falls through and faults cause=1 pc=tval=00001000 cycles=23 D=0 Iheld=0 Dheld=0
PASS fetch-valid ext=1 taken BEQ at 0xffc redirects and squashes fault marker=41 cycles=26 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JAL at 0xffc redirects inward; link survives marker=42 cycles=26 Iheld=0 Dheld=0
PASS fetch-valid ext=1 JALR at 0xffc redirects inward; link survives marker=43 cycles=31 Iheld=0 Dheld=0
PASS fetch-fault ext=1 reset cancels sticky fetch fault and restarts core cause=1 pc=tval=00001000 cycles=18 D=0 Iheld=0 Dheld=0
PASS fetch-reset ext=1 sticky clear and fresh execution
PASS fetch-fault suite ext=1 cases=12 fault=8 valid=4 architectural-checks=12672
tb/tb_fetch_fault.sv:508: $finish called at 66970000 (1ps)
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS expected legacy FAULT_HALT=0 simulator rejection 0
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS expected legacy FAULT_HALT=0 simulator rejection 1
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS expected legacy FAULT_HALT=0 simulator rejection 2
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS expected legacy FAULT_HALT=0 simulator rejection 3
rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
PASS ALU, immediates, forwarding (34 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS loads, stores, RAW stalls (42 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS branches, redirects, flush (53 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS load to branch / flush   (25 cycles to PC past end, 32 regs and 1024 memory words checked)
PASS ALL: 4 integrated RV32I programs, 4224 architectural state checks
Observed: 13 load-use stalls, 11 taken branch redirects
tb/tb_integrated_rv32i.sv:421: $finish called at 1940000 (1ps)
PASS fetch-range FAULT_HALT=1 matrix: 6 configurations, 72 cases (48 sticky fetch faults, 24 valid), 76032 architectural comparisons
PASS fetch-range external backpressure: held I and held D responses observed, no invalid I request offered
PASS fetch-range FAULT_HALT=0 legacy: 4 expected simulator rejections + 4 integrated programs (4224 historical checks)
Actual VCD: <scratch-output-dir>/fetch_fault_handshakes.vcd
Run logs and compiled simulations: <scratch-output-dir>