--- fault halt mode0_d1x0_i2x2_extd3x2_r1_h0 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=0 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=8 PASS fault halt ext=0 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=4 PASS fault halt ext=0 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=4 PASS fault halt ext=0 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=6 PASS fault halt ext=0 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=6 PASS fault halt ext=0 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=6 PASS fault halt ext=0 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=6 PASS fault halt ext=0 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=4 PASS fault halt ext=0 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=5 PASS fault halt ext=0 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS fault halt ext=0 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=3 PASS fault halt ext=0 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS no-fault ext=0 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=13 PASS no-fault ext=0 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=10 PASS no-fault ext=0 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=17 PASS fault-halt regression ext=0 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 9640000 (1ps) --- fault halt mode0_d2x3_i2x2_extd3x2_r1_h0 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=0 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=11 PASS fault halt ext=0 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=4 PASS fault halt ext=0 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=4 PASS fault halt ext=0 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=7 PASS fault halt ext=0 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=7 PASS fault halt ext=0 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=7 PASS fault halt ext=0 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=7 PASS fault halt ext=0 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=4 PASS fault halt ext=0 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=5 PASS fault halt ext=0 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS fault halt ext=0 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=3 PASS fault halt ext=0 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS no-fault ext=0 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=20 PASS no-fault ext=0 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=10 PASS no-fault ext=0 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=31 PASS fault-halt regression ext=0 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 11480000 (1ps) --- fault halt mode0_d4x3_i2x2_extd3x2_r1_h0 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=0 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=15 PASS fault halt ext=0 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=4 PASS fault halt ext=0 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=4 PASS fault halt ext=0 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=9 PASS fault halt ext=0 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=9 PASS fault halt ext=0 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=9 PASS fault halt ext=0 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=9 PASS fault halt ext=0 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=4 PASS fault halt ext=0 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=5 PASS fault halt ext=0 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS fault halt ext=0 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=3 PASS fault halt ext=0 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=4 PASS no-fault ext=0 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=24 PASS no-fault ext=0 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=10 PASS no-fault ext=0 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=41 PASS fault-halt regression ext=0 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 12520000 (1ps) --- fault halt mode1_d1x0_i2x2_extd3x2_r1_h0 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=1 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=37 PASS fault halt ext=1 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=16 PASS fault halt ext=1 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=16 PASS fault halt ext=1 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=26 PASS fault halt ext=1 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=26 PASS fault halt ext=1 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=26 PASS fault halt ext=1 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=26 PASS fault halt ext=1 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=16 PASS fault halt ext=1 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=24 PASS fault halt ext=1 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=16 PASS fault halt ext=1 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=9 PASS fault halt ext=1 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=16 PASS no-fault ext=1 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=55 PASS no-fault ext=1 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=40 PASS no-fault ext=1 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=80 PASS fault-halt regression ext=1 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 12930000 (1ps) --- fault halt mode1_d2x3_i4x3_extd1x4_r1_h3 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=1 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=42 PASS fault halt ext=1 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=20 PASS fault halt ext=1 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=20 PASS fault halt ext=1 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=31 PASS fault halt ext=1 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=31 PASS fault halt ext=1 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=31 PASS fault halt ext=1 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=31 PASS fault halt ext=1 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=20 PASS fault halt ext=1 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=30 PASS fault halt ext=1 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=20 PASS fault halt ext=1 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=11 PASS fault halt ext=1 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=20 PASS no-fault ext=1 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=60 PASS no-fault ext=1 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=50 PASS no-fault ext=1 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=86 PASS fault-halt regression ext=1 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 16850000 (1ps) --- fault halt mode1_d4x3_i1x0_extd6x2_r1_h4 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS fault halt ext=1 illegal opcode after older SW/LW cause=2 pc=0000000c tval=ffffffff D=2 cycles=40 PASS fault halt ext=1 illegal reserved shift encoding cause=2 pc=00000004 tval=40009093 D=0 cycles=13 PASS fault halt ext=1 illegal reserved load funct3 cause=2 pc=00000004 tval=00003103 D=0 cycles=13 PASS fault halt ext=1 misaligned LH byte address 1 cause=4 pc=00000008 tval=00000001 D=1 cycles=25 PASS fault halt ext=1 misaligned LW byte address 2 cause=4 pc=00000008 tval=00000002 D=1 cycles=25 PASS fault halt ext=1 misaligned SH byte address 3 cause=6 pc=00000008 tval=00000003 D=1 cycles=25 PASS fault halt ext=1 misaligned SW byte address 2 cause=6 pc=00000008 tval=00000002 D=1 cycles=25 PASS fault halt ext=1 LW beyond modeled 4KiB RAM cause=5 pc=00000004 tval=00001000 D=0 cycles=13 PASS fault halt ext=1 SW beyond modeled 4KiB RAM cause=7 pc=00000008 tval=00001000 D=0 cycles=18 PASS fault halt ext=1 JALR resolved target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=13 PASS fault halt ext=1 JAL target not 4-byte aligned cause=0 pc=00000000 tval=00000002 D=0 cycles=8 PASS fault halt ext=1 taken BEQ target not 4-byte aligned cause=0 pc=00000004 tval=00000006 D=0 cycles=13 PASS no-fault ext=1 wrong-path illegal and bad memory ignored marker=42 D=2 cycles=50 PASS no-fault ext=1 wrong-path misaligned JALR and SW ignored marker=43 D=0 cycles=30 PASS no-fault ext=1 valid last-word/half/byte memory boundaries marker=44 D=5 cycles=90 PASS fault-halt regression ext=1 scenarios=15 fault-cases=12 state-checks=15840 tb/tb_fault_halt.sv:490: $finish called at 16550000 (1ps) --- legacy unsupported memory access fatal 0 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS legacy fatal case=0 --- legacy unsupported memory access fatal 1 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS legacy fatal case=1 --- legacy unsupported memory access fatal 2 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS legacy fatal case=2 --- legacy unsupported memory access fatal 3 --- rtl/control_unit.sv:49: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/alu.sv:12: sorry: constant selects in always_* processes are not currently supported (all bits will be included). rtl/control_unit.sv:27: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/control_unit.sv:52: vvp.tgt sorry: Case unique/unique0 qualities are ignored. rtl/alu.sv:16: vvp.tgt sorry: Case unique/unique0 qualities are ignored. PASS legacy fatal case=3 PASS FAULT_HALT matrix: 6 configurations, 90 scenarios (95040 architectural state comparisons) PASS FAULT_HALT legacy: 4 expected simulator-fatal memory access rejections Logs and simulation builds: