External I/D bus regression, Icarus Verilog 12, Oct 14 2026 Tested source tree 27edab79d73bc0d881e9a9621f621497b603d1c5 Reproduce: bash scripts/run_regression.sh /tmp/rv32i-evidence Actual simulator stdout follows; only absolute host paths replaced. --- alu --- VCD info: dumpfile alu_sim.vcd opened for output. tb_alu PASS /tb/tb_alu.sv:71: $finish called at 11000 (1ps) --- register_file --- VCD info: dumpfile register_file_sim.vcd opened for output. tb_register_file PASS /tb/tb_register_file.sv:115: $finish called at 67000 (1ps) --- control_unit --- VCD info: dumpfile control_unit_sim.vcd opened for output. tb_control_unit PASS /tb/tb_control_unit.sv:82: $finish called at 9000 (1ps) --- integrated architectural programs --- Writing integrated RV32I waveform to /rv32i_integrated.vcd VCD info: dumpfile /rv32i_integrated.vcd opened for output. PASS ALU, immediates, forwarding (34 cycles to PC past end, 32 regs and 1024 memory words checked) PASS loads, stores, RAW stalls (42 cycles to PC past end, 32 regs and 1024 memory words checked) PASS branches, redirects, flush (53 cycles to PC past end, 32 regs and 1024 memory words checked) PASS load to branch / flush (25 cycles to PC past end, 32 regs and 1024 memory words checked) PASS ALL: 4 integrated RV32I programs, 4224 architectural state checks Observed: 13 load-use stalls, 11 taken branch redirects /tb/tb_integrated_rv32i.sv:421: $finish called at 1940000 (1ps) --- independent control-flow program --- VCD info: dumpfile rv32i_controlflow.vcd opened for output. PASS controlflow: U/J, signed/unsigned branches, redirect flush, JALR alignment, x0 /tb/tb_controlflow_rv32i.sv:60: $finish called at 930000 (1ps) PASS regression: 3 standalone modules + 4 integrated programs + 1 control-flow program --- latency-aware memory and independent reference regressions --- --- Directed memory latency 1 extra 0 --- PASS DATA_LATENCY=1 extra=0 back-to-back LW/SW, RAW and address cycles=36 req/rsp=12/12 stores=6 PASS DATA_LATENCY=1 extra=0 consecutive delayed loads and stores cycles=29 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=0 loads + redirect + wrong-path stores cycles=43 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=0 loaded loop bound and backward branch cycles=30 req/rsp=5/5 stores=2 PASS DATA_LATENCY=1 extra=0 reset during pending memory store cycles=13 req/rsp=3/3 stores=1 PASS DATA_LATENCY=1 extra=0 byte/halfword sign extension and lanes cycles=45 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=1 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 3260000 (1ps) --- Directed memory latency 1 extra 3 --- PASS DATA_LATENCY=1 extra=3 back-to-back LW/SW, RAW and address cycles=52 req/rsp=12/12 stores=6 PASS DATA_LATENCY=1 extra=3 consecutive delayed loads and stores cycles=38 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=3 loads + redirect + wrong-path stores cycles=52 req/rsp=9/9 stores=3 PASS DATA_LATENCY=1 extra=3 loaded loop bound and backward branch cycles=36 req/rsp=5/5 stores=2 PASS DATA_LATENCY=1 extra=3 reset during pending memory store cycles=16 req/rsp=3/3 stores=1 PASS DATA_LATENCY=1 extra=3 byte/halfword sign extension and lanes cycles=75 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=1 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 3990000 (1ps) --- Directed memory latency 2 extra 0 --- PASS DATA_LATENCY=2 extra=0 back-to-back LW/SW, RAW and address cycles=48 req/rsp=12/12 stores=6 PASS DATA_LATENCY=2 extra=0 consecutive delayed loads and stores cycles=38 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=0 loads + redirect + wrong-path stores cycles=52 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=0 loaded loop bound and backward branch cycles=35 req/rsp=5/5 stores=2 PASS DATA_LATENCY=2 extra=0 reset during pending memory store cycles=16 req/rsp=3/3 stores=1 PASS DATA_LATENCY=2 extra=0 byte/halfword sign extension and lanes cycles=64 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=2 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 4080000 (1ps) --- Directed memory latency 2 extra 3 --- PASS DATA_LATENCY=2 extra=3 back-to-back LW/SW, RAW and address cycles=64 req/rsp=12/12 stores=6 PASS DATA_LATENCY=2 extra=3 consecutive delayed loads and stores cycles=47 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=3 loads + redirect + wrong-path stores cycles=61 req/rsp=9/9 stores=3 PASS DATA_LATENCY=2 extra=3 loaded loop bound and backward branch cycles=41 req/rsp=5/5 stores=2 PASS DATA_LATENCY=2 extra=3 reset during pending memory store cycles=19 req/rsp=3/3 stores=1 PASS DATA_LATENCY=2 extra=3 byte/halfword sign extension and lanes cycles=94 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=2 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 4810000 (1ps) --- Directed memory latency 4 extra 0 --- PASS DATA_LATENCY=4 extra=0 back-to-back LW/SW, RAW and address cycles=72 req/rsp=12/12 stores=6 PASS DATA_LATENCY=4 extra=0 consecutive delayed loads and stores cycles=56 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=0 loads + redirect + wrong-path stores cycles=70 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=0 loaded loop bound and backward branch cycles=45 req/rsp=5/5 stores=2 PASS DATA_LATENCY=4 extra=0 reset during pending memory store cycles=22 req/rsp=3/3 stores=1 PASS DATA_LATENCY=4 extra=0 byte/halfword sign extension and lanes cycles=102 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=4 DATA_MAX_EXTRA=0 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 5700000 (1ps) --- Directed memory latency 4 extra 3 --- PASS DATA_LATENCY=4 extra=3 back-to-back LW/SW, RAW and address cycles=88 req/rsp=12/12 stores=6 PASS DATA_LATENCY=4 extra=3 consecutive delayed loads and stores cycles=65 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=3 loads + redirect + wrong-path stores cycles=79 req/rsp=9/9 stores=3 PASS DATA_LATENCY=4 extra=3 loaded loop bound and backward branch cycles=51 req/rsp=5/5 stores=2 PASS DATA_LATENCY=4 extra=3 reset during pending memory store cycles=25 req/rsp=3/3 stores=1 PASS DATA_LATENCY=4 extra=3 byte/halfword sign extension and lanes cycles=132 req/rsp=19/19 stores=4 PASS latency-controlled memory RV32I: DATA_LATENCY=4 DATA_MAX_EXTRA=3 cases=6 checks=6336 /tb/tb_memory_latency_rv32i.sv:498: $finish called at 6430000 (1ps) SEED 31415: 198 instructions, 191 sequential reference steps --- Reference seed 31415 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=333 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3620000 (1ps) --- Reference seed 31415 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=438 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4700000 (1ps) --- Reference seed 31415 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=506 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 5390000 (1ps) --- Reference seed 31415 latency 4 extra 3 --- VCD info: dumpfile /memory/memory_handshake.vcd opened for output. PASS random reference latency=4 extra=3 cycles=642 requests=68 responses=68 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6770000 (1ps) SEED 27182: 202 instructions, 194 sequential reference steps --- Reference seed 27182 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=328 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3570000 (1ps) --- Reference seed 27182 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=420 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4520000 (1ps) --- Reference seed 27182 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=479 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 5120000 (1ps) --- Reference seed 27182 latency 4 extra 3 --- PASS random reference latency=4 extra=3 cycles=597 requests=59 responses=59 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6320000 (1ps) SEED 16180: 196 instructions, 188 sequential reference steps --- Reference seed 16180 latency 1 extra 0 --- PASS random reference latency=1 extra=0 cycles=321 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 3500000 (1ps) --- Reference seed 16180 latency 1 extra 3 --- PASS random reference latency=1 extra=3 cycles=408 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4400000 (1ps) --- Reference seed 16180 latency 2 extra 3 --- PASS random reference latency=2 extra=3 cycles=464 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 4970000 (1ps) --- Reference seed 16180 latency 4 extra 3 --- PASS random reference latency=4 extra=3 cycles=576 requests=56 responses=56 1056 architectural checks /tb/tb_random_reference_rv32i.sv:68: $finish called at 6110000 (1ps) --- Expected simulation rejection: memory fault 0 --- PASS expected rejection fault 0 --- Expected simulation rejection: memory fault 1 --- PASS expected rejection fault 1 --- Expected simulation rejection: memory fault 2 --- PASS expected rejection fault 2 --- Expected simulation rejection: memory fault 3 --- PASS expected rejection fault 3 PASS memory regression: 36 directed scenario runs (38016 state checks), 12 reference-program runs (12672 state checks), 4 expected fault rejections Actual logs and VCD: /memory --- independently timed external instruction/data interfaces --- SEED 31415: 198 instructions, 191 sequential reference steps SEED 27182: 202 instructions, 194 sequential reference steps SEED 16180: 196 instructions, 188 sequential reference steps --- independent buses i2x2_d3x3_r1_h0 --- PASS external mixed stores, loads and byte lanes cycles=142 I=20/19 D=10/10 stores=5 Iwait=5 Dwait=6 Iheld=37 Dheld=0 PASS external branch redirects and wrong-path suppression cycles=123 I=20/19 D=5/5 stores=2 Iwait=6 Dwait=2 Iheld=23 Dheld=0 PASS external backward branch with delayed fetch cycles=140 I=24/23 D=3/3 stores=1 Iwait=7 Dwait=3 Iheld=12 Dheld=0 PASS external signed subword loads and masked stores cycles=125 I=18/17 D=10/10 stores=2 Iwait=3 Dwait=3 Iheld=35 Dheld=0 PASS external reset aborts pending external store cycles=51 I=11/10 D=3/3 stores=1 Iwait=2 Dwait=0 Iheld=12 Dheld=0 PASS external 300 redirect loop, 8-bit epoch wrap cycles=8337 I=1207/1206 D=0/0 stores=0 Iwait=301 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=2194 I=308/307 D=0/0 stores=0 Iwait=96 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(2+2) D(3+3) throttle=1 response-delay=0 /tb/tb_external_bus_rv32i.sv:463: $finish called at 114090000 (1ps) --- independent Python oracle seed 31415 i2x2_d3x3_r1_h0 --- PASS external Python oracle nins=198 cycles=1730 checks=1056 I=214/213 D=68/68 writes=34 PASS external-bus RV32I cases=1 state-checks=1056 I(2+2) D(3+3) throttle=1 response-delay=0 /tb/tb_external_bus_rv32i.sv:463: $finish called at 17890000 (1ps) --- independent Python oracle seed 27182 i2x2_d3x3_r1_h0 --- PASS external Python oracle nins=202 cycles=1743 checks=1056 I=218/217 D=59/59 writes=25 PASS external-bus RV32I cases=1 state-checks=1056 I(2+2) D(3+3) throttle=1 response-delay=0 /tb/tb_external_bus_rv32i.sv:463: $finish called at 18020000 (1ps) --- independent Python oracle seed 16180 i2x2_d3x3_r1_h0 --- PASS external Python oracle nins=196 cycles=1667 checks=1056 I=212/211 D=56/56 writes=18 PASS external-bus RV32I cases=1 state-checks=1056 I(2+2) D(3+3) throttle=1 response-delay=0 /tb/tb_external_bus_rv32i.sv:463: $finish called at 17260000 (1ps) --- independent buses i2x4_d1x2_r1_h3 --- VCD info: dumpfile /external/external_bus.vcd opened for output. PASS external mixed stores, loads and byte lanes cycles=133 I=21/20 D=10/10 stores=5 Iwait=3 Dwait=8 Iheld=16 Dheld=9 PASS external branch redirects and wrong-path suppression cycles=126 I=21/20 D=5/5 stores=2 Iwait=6 Dwait=0 Iheld=7 Dheld=4 PASS external backward branch with delayed fetch cycles=151 I=24/24 D=3/3 stores=1 Iwait=7 Dwait=2 Iheld=9 Dheld=6 PASS external signed subword loads and masked stores cycles=118 I=19/18 D=10/10 stores=2 Iwait=6 Dwait=8 Iheld=16 Dheld=12 PASS external reset aborts pending external store cycles=48 I=12/11 D=3/3 stores=1 Iwait=3 Dwait=1 Iheld=2 Dheld=1 PASS external 300 redirect loop, 8-bit epoch wrap cycles=9455 I=1207/1207 D=0/0 stores=0 Iwait=299 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=2419 I=309/308 D=0/0 stores=0 Iwait=38 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(2+4) D(1+2) throttle=1 response-delay=3 /tb/tb_external_bus_rv32i.sv:463: $finish called at 128240000 (1ps) --- independent Python oracle seed 31415 i2x4_d1x2_r1_h3 --- PASS external Python oracle nins=198 cycles=1783 checks=1056 I=214/213 D=68/68 writes=34 PASS external-bus RV32I cases=1 state-checks=1056 I(2+4) D(1+2) throttle=1 response-delay=3 /tb/tb_external_bus_rv32i.sv:463: $finish called at 18500000 (1ps) --- independent Python oracle seed 27182 i2x4_d1x2_r1_h3 --- PASS external Python oracle nins=202 cycles=1793 checks=1056 I=219/218 D=59/59 writes=25 PASS external-bus RV32I cases=1 state-checks=1056 I(2+4) D(1+2) throttle=1 response-delay=3 /tb/tb_external_bus_rv32i.sv:463: $finish called at 18600000 (1ps) --- independent Python oracle seed 16180 i2x4_d1x2_r1_h3 --- PASS external Python oracle nins=196 cycles=1746 checks=1056 I=212/212 D=56/56 writes=18 PASS external-bus RV32I cases=1 state-checks=1056 I(2+4) D(1+2) throttle=1 response-delay=3 /tb/tb_external_bus_rv32i.sv:463: $finish called at 18130000 (1ps) --- independent buses i5x2_d4x1_r1_h5 --- PASS external mixed stores, loads and byte lanes cycles=161 I=20/20 D=10/10 stores=5 Iwait=7 Dwait=6 Iheld=13 Dheld=7 PASS external branch redirects and wrong-path suppression cycles=151 I=20/20 D=5/5 stores=2 Iwait=6 Dwait=0 Iheld=9 Dheld=3 PASS external backward branch with delayed fetch cycles=185 I=24/23 D=3/3 stores=1 Iwait=8 Dwait=0 Iheld=2 Dheld=2 PASS external signed subword loads and masked stores cycles=142 I=19/18 D=10/10 stores=2 Iwait=8 Dwait=5 Iheld=11 Dheld=5 PASS external reset aborts pending external store cycles=60 I=11/10 D=3/3 stores=1 Iwait=6 Dwait=2 Iheld=5 Dheld=2 PASS external 300 redirect loop, 8-bit epoch wrap cycles=12018 I=1207/1207 D=0/0 stores=0 Iwait=379 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=3176 I=308/308 D=0/0 stores=0 Iwait=174 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(5+2) D(4+1) throttle=1 response-delay=5 /tb/tb_external_bus_rv32i.sv:463: $finish called at 163490000 (1ps) --- independent Python oracle seed 31415 i5x2_d4x1_r1_h5 --- PASS external Python oracle nins=198 cycles=2195 checks=1056 I=213/213 D=68/68 writes=34 PASS external-bus RV32I cases=1 state-checks=1056 I(5+2) D(4+1) throttle=1 response-delay=5 /tb/tb_external_bus_rv32i.sv:463: $finish called at 22710000 (1ps) --- independent Python oracle seed 27182 i5x2_d4x1_r1_h5 --- PASS external Python oracle nins=202 cycles=2254 checks=1056 I=217/217 D=59/59 writes=25 PASS external-bus RV32I cases=1 state-checks=1056 I(5+2) D(4+1) throttle=1 response-delay=5 /tb/tb_external_bus_rv32i.sv:463: $finish called at 23300000 (1ps) --- independent Python oracle seed 16180 i5x2_d4x1_r1_h5 --- PASS external Python oracle nins=196 cycles=2154 checks=1056 I=211/210 D=56/56 writes=18 PASS external-bus RV32I cases=1 state-checks=1056 I(5+2) D(4+1) throttle=1 response-delay=5 /tb/tb_external_bus_rv32i.sv:463: $finish called at 22300000 (1ps) --- independent buses i1x0_d6x2_r1_h2 --- PASS external mixed stores, loads and byte lanes cycles=162 I=23/22 D=10/10 stores=5 Iwait=7 Dwait=6 Iheld=84 Dheld=0 PASS external branch redirects and wrong-path suppression cycles=120 I=23/22 D=5/5 stores=2 Iwait=7 Dwait=5 Iheld=45 Dheld=0 PASS external backward branch with delayed fetch cycles=118 I=27/26 D=3/3 stores=1 Iwait=9 Dwait=2 Iheld=22 Dheld=0 PASS external signed subword loads and masked stores cycles=147 I=21/20 D=10/10 stores=2 Iwait=7 Dwait=4 Iheld=79 Dheld=0 PASS external reset aborts pending external store cycles=57 I=14/14 D=3/3 stores=1 Iwait=5 Dwait=0 Iheld=25 Dheld=0 PASS external 300 redirect loop, 8-bit epoch wrap cycles=6011 I=1210/1209 D=0/0 stores=0 Iwait=304 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=1615 I=311/310 D=0/0 stores=0 Iwait=104 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(1+0) D(6+2) throttle=1 response-delay=2 /tb/tb_external_bus_rv32i.sv:463: $finish called at 85720000 (1ps) --- independent buses i3x3_d3x2_r0_h4 --- PASS external mixed stores, loads and byte lanes cycles=140 I=21/20 D=10/10 stores=5 Iwait=0 Dwait=0 Iheld=19 Dheld=3 PASS external branch redirects and wrong-path suppression cycles=133 I=21/20 D=5/5 stores=2 Iwait=0 Dwait=0 Iheld=10 Dheld=1 PASS external backward branch with delayed fetch cycles=154 I=25/24 D=3/3 stores=1 Iwait=0 Dwait=0 Iheld=5 Dheld=3 PASS external signed subword loads and masked stores cycles=120 I=19/18 D=10/10 stores=2 Iwait=0 Dwait=0 Iheld=14 Dheld=4 PASS external reset aborts pending external store cycles=52 I=12/11 D=3/3 stores=1 Iwait=0 Dwait=0 Iheld=7 Dheld=0 PASS external 300 redirect loop, 8-bit epoch wrap cycles=9912 I=1208/1207 D=0/0 stores=0 Iwait=0 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=2569 I=309/308 D=0/0 stores=0 Iwait=0 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(3+3) D(3+2) throttle=0 response-delay=4 /tb/tb_external_bus_rv32i.sv:463: $finish called at 134960000 (1ps) --- independent buses i7x3_d2x4_r1_h6 --- PASS external mixed stores, loads and byte lanes cycles=186 I=20/19 D=10/10 stores=5 Iwait=8 Dwait=7 Iheld=2 Dheld=28 PASS external branch redirects and wrong-path suppression cycles=187 I=20/19 D=5/5 stores=2 Iwait=8 Dwait=2 Iheld=3 Dheld=5 PASS external backward branch with delayed fetch cycles=229 I=24/23 D=3/3 stores=1 Iwait=9 Dwait=2 Iheld=1 Dheld=9 PASS external signed subword loads and masked stores cycles=160 I=18/17 D=10/10 stores=2 Iwait=10 Dwait=4 Iheld=0 Dheld=22 PASS external reset aborts pending external store cycles=68 I=11/10 D=3/3 stores=1 Iwait=6 Dwait=2 Iheld=0 Dheld=1 PASS external 300 redirect loop, 8-bit epoch wrap cycles=15016 I=1207/1206 D=0/0 stores=0 Iwait=302 Dwait=0 Iheld=0 Dheld=0 PASS external 301 sequential instructions across fetch cycles=3929 I=308/307 D=0/0 stores=0 Iwait=154 Dwait=0 Iheld=0 Dheld=0 PASS external-bus RV32I cases=7 state-checks=7392 I(7+3) D(2+4) throttle=1 response-delay=6 /tb/tb_external_bus_rv32i.sv:463: $finish called at 202920000 (1ps) --- independent Python oracle seed 31415 i7x3_d2x4_r1_h6 --- PASS external Python oracle nins=198 cycles=2660 checks=1056 I=213/212 D=68/68 writes=34 PASS external-bus RV32I cases=1 state-checks=1056 I(7+3) D(2+4) throttle=1 response-delay=6 /tb/tb_external_bus_rv32i.sv:463: $finish called at 27430000 (1ps) --- independent Python oracle seed 27182 i7x3_d2x4_r1_h6 --- PASS external Python oracle nins=202 cycles=2717 checks=1056 I=216/216 D=59/59 writes=25 PASS external-bus RV32I cases=1 state-checks=1056 I(7+3) D(2+4) throttle=1 response-delay=6 /tb/tb_external_bus_rv32i.sv:463: $finish called at 28000000 (1ps) --- independent Python oracle seed 16180 i7x3_d2x4_r1_h6 --- PASS external Python oracle nins=196 cycles=2636 checks=1056 I=211/210 D=56/56 writes=18 PASS external-bus RV32I cases=1 state-checks=1056 I(7+3) D(2+4) throttle=1 response-delay=6 /tb/tb_external_bus_rv32i.sv:463: $finish called at 27190000 (1ps) --- expected corrupt I response tag rejection --- PASS rejected invalid I response tag --- expected corrupt D response tag rejection --- PASS rejected invalid D response tag PASS external directed: 42 architectural scenario runs (44352 state comparisons), six independent I/D timing configurations PASS external oracle: 12 independently interpreted runs (12672 state comparisons) PASS external protocol faults: 2 expected response identity rejections Actual external waveform and test logs: /external Evidence and logs: